Pyverilog 0.7.0

Author: shtaxxx

.gitignore

@@ -0,0 +1,3 @@
+*.pyc
+*.out
+parsetab.py

Makefile

@@ -1,31 +1,15 @@
 .PHONY: all
 all:
 	make -C ./vparser
-	make -C ./definition_analyzer
-	make -C ./definition_resolver
-	make -C ./optimizer
-	make -C ./tree_constructor
-	make -C ./tree_walker
-	make -C ./graph
-	make -C ./subset
-	make -C ./codegen	
+	make -C ./dataflow
 	make -C ./controlflow
-	make -C ./active_condition
-	make -C ./ast_to_code
+	make -C ./ast_code_generator
 
 .PHONY: clean
 clean:
 	make clean -C ./utils
 	make clean -C ./vparser
-	make clean -C ./definition_analyzer
-	make clean -C ./definition_resolver
-	make clean -C ./optimizer
-	make clean -C ./tree_constructor
-	make clean -C ./tree_walker
-	make clean -C ./graph
-	make clean -C ./subset
-	make clean -C ./codegen	
+	make clean -C ./dataflow
 	make clean -C ./controlflow
-	make clean -C ./active_condition
-	make clean -C ./ast_to_code
+	make clean -C ./ast_code_generator
 	rm -rf *.pyc __pycache__ *.out parsetab.py *.html

README.md

@@ -2,14 +2,6 @@
 if sys.version_info[0] < 3:
     import utils
     import vparser
-    import definition_analyzer
-    import definition_resolver
-    import optimizer
-    import tree_constructor
-    import tree_walker
-    import graph
-    import subset
-    import codegen	
+    import dataflow
     import controlflow
-    import active_condition
-    #import ast_to_code # Python 2.x does not support
+    #import ast_code_generator # Python 2.7 does not support

__init__.py

@@ -0,0 +1,13 @@
+PYTHON=python3.3
+#OPT=-m pdb
+
+CODEGEN=codegen.py
+SRCS=../testcode/generate.v
+
+.PHONY: codegen
+codegen:
+	$(PYTHON) $(OPT) $(CODEGEN) $(SRCS)
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

active_condition/Makefile

@@ -1,7 +1,7 @@
 #-------------------------------------------------------------------------------
-# ast_to_code.py
+# codegen.py
 # 
-# AST to Verilog HDL source code
+# Code Generator from AST to Verilog HDL source code
 #
 # Copyright (C) 2013, Shinya Takamaeda-Yamazaki
 # License: Apache 2.0
@@ -11,7 +11,7 @@
 import os
 import math
 import re
-from jinja2 import Environment, PackageLoader
+from jinja2 import Environment, FileSystemLoader
 
 sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
 
@@ -36,9 +36,9 @@ def generic_visit(self, node):
 def getfilename(node):
     return node.__class__.__name__.lower() + '.txt'
 
-class ASTtoCode(ConvertVisitor):
+class ASTCodeGenerator(ConvertVisitor):
     def __init__(self):
-        self.env = Environment(loader=PackageLoader('pyverilog.ast_to_code','template'))
+        self.env = Environment(loader=FileSystemLoader(DEFAULT_TEMPLATE_DIR))
 
     def visit_Source(self, node):
         filename = getfilename(node)
@@ -939,9 +939,9 @@ def visit_SingleStatement(self, node):
 if __name__ == '__main__':
     from optparse import OptionParser
 
-    INFO = "Verilog AST to code converter with Pyverilog"
+    INFO = "Code converter from AST"
     VERSION = pyverilog.utils.version.VERSION
-    USAGE = "Usage: python ast_to_code.py file ..."
+    USAGE = "Usage: python codegen.py file ..."
 
     def showVersion():
         print(INFO)
@@ -970,6 +970,7 @@ def showVersion():
     ast = codeparser.parse()
     directives = codeparser.get_directives()
 
-    asttocode = ASTtoCode()
-    rslt = asttocode.visit(ast)
+    codegen = ASTCodeGenerator()
+    rslt = codegen.visit(ast)
     print(rslt)
+