AST node start position and end position support

[jinfuchen]

Hi,

Thanks for the practical tool to parse Verilog. I am wondering whether Pyverilog supports returning start and end position of each node.
If not, any API I can use to extract such information?

Thanks.

[leonardt]

I've only used this with the ModuleDef node, but a quick scan of the code (https://github.com/PyHDI/Pyverilog/blob/d78ee0f2004cbc0b370d20c20b1bac31f55c41a5/pyverilog/vparser/parser.py and https://github.com/PyHDI/Pyverilog/blob/a1bf312e9608ba47d3724dacbb98928b66ef561c/pyverilog/vparser/ast.py for example) it seems that most nodes provide the lineno attribute for the line number, the moduledef node also provides an end_lineno attribute for the end.

[jinfuchen]

Thanks for your hint :)
I read the code. Yeah, we can get the line number of each node in the AST. However, I still want to extract the exact start and end position of each node like ASTNode provided by JDT, since I want to compare two ASTs of Verilog.
Do you @leonardt think we can use Pyverilog to get this step? Or any other parser?
Thanks.