patch v1.3.4 (#377)

* Create HOWTO_detect_power_gated_AFI.md

* Update strategy_TIMING.tcl

* Update RTL_Simulating_CL_Designs.md

Author: kristopk

hdk/common/shell_v071417d3/build/scripts/strategy_TIMING.tcl

@@ -1,7 +1,7 @@
 source $HDK_SHELL_DIR/build/scripts/params.tcl
 source $HDK_SHELL_DIR/build/scripts/uram_options.tcl
 
-set synth_options "-no_lc -shreg_min_size 5 -fsm_extraction one_hot -resource_sharing off $synth_uram_option"
+set synth_options "-no_lc -shreg_min_size 5 -fsm_extraction one_hot -resource_sharing auto $synth_uram_option"
 set synth_directive "default"
 
 #Set psip to 1 to enable Physical Synthesis in Placer (2017.1+ only)

hdk/docs/HOWTO_detect_power_gated_AFI.md

@@ -0,0 +1,10 @@
+# AFI Power Gating
+ 
+* The Xilinx UltraScale+ FPGA devices used on the F1 instances have power limits that must be maintained.
+* An AFI that tripped an over-current will be clock gated and will show the following effects:
+   * AFI fpga-load-local-image will cause cl-id-mismatch (Any AFI load will show this error including the AWS public AFIs)
+   * Transactions to CL will trigger timeouts on all Shell to CL interfaces
+   * AFI fpga-clear-local-image will also fail and not clear the AFI
+   * fpga-describe-local-image won’t necessarily show any failure, except maybe the cl-id-mismatch if you’ve tried to load another AFI.
+* If you see these effects, you can use a lower clock frequency in the clock recipes to reduce the power consumed by the AFI. Recovering from a clock gated AFI requires you to terminate the instance.
+* [Additional information on how to optimize for power](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug907-vivado-power-analysis-optimization.pdf)

hdk/docs/RTL_Simulating_CL_Designs.md

@@ -461,7 +461,7 @@ The SV Test API function 'task peek_pcis' reads 512 bits of data from the CL via
 ## Description
 The SV Test API task 'poke_pcis' writes 512 bits of data to the CL via the AXI PCIE interface.
 ## Declaration
-#### task poke_pcis(input int slot_id = 0, logic [63:0] addr, logic [511:0] data, logic [5:0] id = 6'h0);
+#### task poke_pcis(input int slot_id = 0, logic [63:0] addr, logic [511:0] data, logic [5:0] id = 6'h0, logic [63:0] strb);
 
 | Argument | Description |
 | --- | --- |