diff --git a/test/WaveOps/WaveActiveProduct.fp16.test b/test/WaveOps/WaveActiveProduct.fp16.test
new file mode 100644
index 000000000..5145ee6ec
--- /dev/null
+++ b/test/WaveOps/WaveActiveProduct.fp16.test
@@ -0,0 +1,182 @@
+#--- source.hlsl
+StructuredBuffer<half4> In  : register(t0);
+RWStructuredBuffer<half4> Out1 : register(u1);
+RWStructuredBuffer<half4> Out2 : register(u2);
+RWStructuredBuffer<half4> Out3 : register(u3);
+RWStructuredBuffer<half4> Out4 : register(u4);
+RWStructuredBuffer<half4> Out5 : register(u5);
+
+[numthreads(4,1,1)]
+void main(uint3 tid : SV_GroupThreadID)
+{
+    half4 v = In[0];
+
+    // Mask per "active lane set": only <=N lanes contribute
+    half s1 = tid.x <= 0 ? WaveActiveProduct( v.x ) : 0;
+    half s2 = tid.x <= 1 ? WaveActiveProduct( v.x ) : 0;
+    half s3 = tid.x <= 2 ? WaveActiveProduct( v.x ) : 0;
+    half s4 = tid.x <= 3 ? WaveActiveProduct( v.x ) : 0;
+
+    half2 v2_1 = tid.x <= 0 ? WaveActiveProduct( v.xy ) : half2(0,0);
+    half2 v2_2 = tid.x <= 1 ? WaveActiveProduct( v.xy ) : half2(0,0);
+    half2 v2_3 = tid.x <= 2 ? WaveActiveProduct( v.xy ) : half2(0,0);
+    half2 v2_4 = tid.x <= 3 ? WaveActiveProduct( v.xy ) : half2(0,0);
+
+    half3 v3_1 = tid.x <= 0 ? WaveActiveProduct( v.xyz ) : half3(0,0,0);
+    half3 v3_2 = tid.x <= 1 ? WaveActiveProduct( v.xyz ) : half3(0,0,0);
+    half3 v3_3 = tid.x <= 2 ? WaveActiveProduct( v.xyz ) : half3(0,0,0);
+    half3 v3_4 = tid.x <= 3 ? WaveActiveProduct( v.xyz ) : half3(0,0,0);
+
+    half4 v4_1 = tid.x <= 0 ? WaveActiveProduct( v ) : half4(0,0,0,0);
+    half4 v4_2 = tid.x <= 1 ? WaveActiveProduct( v ) : half4(0,0,0,0);
+    half4 v4_3 = tid.x <= 2 ? WaveActiveProduct( v ) : half4(0,0,0,0);
+    half4 v4_4 = tid.x <= 3 ? WaveActiveProduct( v ) : half4(0,0,0,0);
+
+    half scalars[4] = { s1, s2, s3, s4 };
+    half2 vec2s [4] = { v2_1, v2_2, v2_3, v2_4 };
+    half3 vec3s [4] = { v3_1, v3_2, v3_3, v3_4 };
+    half4 vec4s [4] = { v4_1, v4_2, v4_3, v4_4 };
+
+
+    Out1[tid.x].x   = scalars[tid.x];
+    Out2[tid.x].xy  = vec2s[tid.x];
+    Out3[tid.x].xyz = vec3s[tid.x];
+    Out4[tid.x]     = vec4s[tid.x];
+
+    // constant folding case
+    Out5[0] = WaveActiveProduct(half4(1,2,3,4));
+}
+
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Float16
+    Stride: 8
+    Data: [0x3C00, 0x4000, 0x4400, 0x4800]
+  - Name: Out1
+    Format: Float16
+    Stride: 8
+    FillSize: 32
+  - Name: Out2
+    Format: Float16
+    Stride: 8
+    FillSize: 32
+  - Name: Out3
+    Format: Float16
+    Stride: 8
+    FillSize: 32
+  - Name: Out4
+    Format: Float16
+    Stride: 8
+    FillSize: 32
+  - Name: Out5
+    Format: Float16
+    Stride: 8
+    FillSize: 8
+  - Name: ExpectedOut1
+    Format: Float16
+    Stride: 8
+    Data: [0x3C00, 0x0000, 0x0000, 0x0000, 0x3C00, 0x0000, 0x0000, 0x0000, 0x3C00, 0x0000, 0x0000, 0x0000, 0x3C00, 0x0000, 0x0000, 0x0000]
+  - Name: ExpectedOut2
+    Format: Float16
+    Stride: 8
+    Data: [0x3C00, 0x4000, 0x0000, 0x0000, 0x3C00, 0x4400, 0x0000, 0x0000, 0x3C00, 0x4800, 0x0000, 0x0000, 0x3C00, 0x4C00, 0x0000, 0x0000]
+  - Name: ExpectedOut3
+    Format: Float16
+    Stride: 8
+    Data: [0x3C00, 0x4000, 0x4400, 0x0000, 0x3C00, 0x4400, 0x4C00, 0x0000, 0x3C00, 0x4800, 60x4400, 0x0000, 0x3C00, 0x4C00, 0x5C00, 0x0000]
+  - Name: ExpectedOut4
+    Format: Float16
+    Stride: 8
+    Data: [0x3C00, 0x4000, 0x4400, 0x4800, 0x3C00, 0x4400, 0x4C00, 60x4400, 0x3C00, 0x4800, 60x4400, 510x4000, 0x3C00, 0x4C00, 0x5C00, 0x6C00]
+  - Name: ExpectedOut5
+    Format: Float16
+    Stride: 8
+    Data: [0x3C00, 0x4C00, 0x5510, 0x5C00]
+Results:
+  - Result: ExpectedOut1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: ExpectedOut2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: ExpectedOut3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: ExpectedOut4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: ExpectedOut5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+
+...
+#--- end
+
+# Bug https://github.com/llvm/llvm-project/issues/156775
+# XFAIL: Clang
+
+# Bug https://github.com/llvm/offload-test-suite/issues/393
+# XFAIL: Metal
+
+# REQUIRES: Half
+
+# RUN: split-file %s %t
+# RUN: %dxc_target-enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o
diff --git a/test/WaveOps/WaveActiveProduct.fp32.test b/test/WaveOps/WaveActiveProduct.fp32.test
new file mode 100644
index 000000000..21eb742c4
--- /dev/null
+++ b/test/WaveOps/WaveActiveProduct.fp32.test
@@ -0,0 +1,182 @@
+#--- source.hlsl
+StructuredBuffer<float4> In  : register(t0);
+RWStructuredBuffer<float4> Out1 : register(u1);
+RWStructuredBuffer<float4> Out2 : register(u2);
+RWStructuredBuffer<float4> Out3 : register(u3);
+RWStructuredBuffer<float4> Out4 : register(u4);
+RWStructuredBuffer<float4> Out5 : register(u5);
+
+[numthreads(4,1,1)]
+void main(uint3 tid : SV_GroupThreadID)
+{
+    float4 v = In[0];
+
+    // Mask per "active lane set": only <=N lanes contribute
+    float s1 = tid.x <= 0 ? WaveActiveProduct( v.x ) : 0;
+    float s2 = tid.x <= 1 ? WaveActiveProduct( v.x ) : 0;
+    float s3 = tid.x <= 2 ? WaveActiveProduct( v.x ) : 0;
+    float s4 = tid.x <= 3 ? WaveActiveProduct( v.x ) : 0;
+
+    float2 v2_1 = tid.x <= 0 ? WaveActiveProduct( v.xy ) : float2(0,0);
+    float2 v2_2 = tid.x <= 1 ? WaveActiveProduct( v.xy ) : float2(0,0);
+    float2 v2_3 = tid.x <= 2 ? WaveActiveProduct( v.xy ) : float2(0,0);
+    float2 v2_4 = tid.x <= 3 ? WaveActiveProduct( v.xy ) : float2(0,0);
+
+    float3 v3_1 = tid.x <= 0 ? WaveActiveProduct( v.xyz ) : float3(0,0,0);
+    float3 v3_2 = tid.x <= 1 ? WaveActiveProduct( v.xyz ) : float3(0,0,0);
+    float3 v3_3 = tid.x <= 2 ? WaveActiveProduct( v.xyz ) : float3(0,0,0);
+    float3 v3_4 = tid.x <= 3 ? WaveActiveProduct( v.xyz ) : float3(0,0,0);
+
+    float4 v4_1 = tid.x <= 0 ? WaveActiveProduct( v ) : float4(0,0,0,0);
+    float4 v4_2 = tid.x <= 1 ? WaveActiveProduct( v ) : float4(0,0,0,0);
+    float4 v4_3 = tid.x <= 2 ? WaveActiveProduct( v ) : float4(0,0,0,0);
+    float4 v4_4 = tid.x <= 3 ? WaveActiveProduct( v ) : float4(0,0,0,0);
+
+    float scalars[4] = { s1, s2, s3, s4 };
+    float2 vec2s [4] = { v2_1, v2_2, v2_3, v2_4 };
+    float3 vec3s [4] = { v3_1, v3_2, v3_3, v3_4 };
+    float4 vec4s [4] = { v4_1, v4_2, v4_3, v4_4 };
+
+
+    Out1[tid.x].x   = scalars[tid.x];
+    Out2[tid.x].xy  = vec2s[tid.x];
+    Out3[tid.x].xyz = vec3s[tid.x];
+    Out4[tid.x]     = vec4s[tid.x];
+
+    // constant folding case
+    Out5[0] = WaveActiveProduct(float4(1,2,3,4));
+}
+
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Float32
+    Stride: 16
+    Data: [1.0, 2.0, 4.0, 8.0]
+  - Name: Out1
+    Format: Float32
+    Stride: 16
+    FillSize: 32
+  - Name: Out2
+    Format: Float32
+    Stride: 16
+    FillSize: 32
+  - Name: Out3
+    Format: Float32
+    Stride: 16
+    FillSize: 32
+  - Name: Out4
+    Format: Float32
+    Stride: 16
+    FillSize: 32
+  - Name: Out5
+    Format: Float32
+    Stride: 16
+    FillSize: 8
+  - Name: ExpectedOut1
+    Format: Float32
+    Stride: 16
+    Data: [1.0, 0.0, 0.0, 0.0, 1.0, 0.0, 0.0, 0.0, 1.0, 0.0, 0.0, 0.0, 1.0, 0.0, 0.0, 0.0]
+  - Name: ExpectedOut2
+    Format: Float32
+    Stride: 16
+    Data: [1.0, 2.0, 0.0, 0.0, 1.0, 4.0, 0.0, 0.0, 1.0, 8.0, 0.0, 0.0, 1.0, 16.0, 0.0, 0.0]
+  - Name: ExpectedOut3
+    Format: Float32
+    Stride: 16
+    Data: [1.0, 2.0, 4.0, 0.0, 1.0, 4.0, 16.0, 0.0, 1.0, 8.0, 64.0, 0.0, 1.0, 16.0, 256.0, 0.0]
+  - Name: ExpectedOut4
+    Format: Float32
+    Stride: 16
+    Data: [1.0, 2.0, 4.0, 8.0, 1.0, 4.0, 16.0, 64.0, 1.0, 8.0, 64.0, 512.0, 1.0, 16.0, 256.0, 4096.0]
+  - Name: ExpectedOut5
+    Format: Float32
+    Stride: 16
+    Data: [1.0, 16.0, 81.0, 256.0]
+Results:
+  - Result: ExpectedOut1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: ExpectedOut2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: ExpectedOut3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: ExpectedOut4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: ExpectedOut5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+
+...
+#--- end
+
+# Bug https://github.com/llvm/llvm-project/issues/156775
+# XFAIL: Clang
+
+# Bug https://github.com/llvm/offload-test-suite/issues/393
+# XFAIL: Metal
+
+
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o
diff --git a/test/WaveOps/WaveActiveProduct.fp64.test b/test/WaveOps/WaveActiveProduct.fp64.test
new file mode 100644
index 000000000..7a4af0f0e
--- /dev/null
+++ b/test/WaveOps/WaveActiveProduct.fp64.test
@@ -0,0 +1,182 @@
+#--- source.hlsl
+StructuredBuffer<double4> In  : register(t0);
+RWStructuredBuffer<double4> Out1 : register(u1);
+RWStructuredBuffer<double4> Out2 : register(u2);
+RWStructuredBuffer<double4> Out3 : register(u3);
+RWStructuredBuffer<double4> Out4 : register(u4);
+RWStructuredBuffer<double4> Out5 : register(u5);
+
+[numthreads(4,1,1)]
+void main(uint3 tid : SV_GroupThreadID)
+{
+    double4 v = In[0];
+
+    // Mask per "active lane set": only <=N lanes contribute
+    double s1 = tid.x <= 0 ? WaveActiveProduct( v.x ) : 0;
+    double s2 = tid.x <= 1 ? WaveActiveProduct( v.x ) : 0;
+    double s3 = tid.x <= 2 ? WaveActiveProduct( v.x ) : 0;
+    double s4 = tid.x <= 3 ? WaveActiveProduct( v.x ) : 0;
+
+    double2 v2_1 = tid.x <= 0 ? WaveActiveProduct( v.xy ) : double2(0,0);
+    double2 v2_2 = tid.x <= 1 ? WaveActiveProduct( v.xy ) : double2(0,0);
+    double2 v2_3 = tid.x <= 2 ? WaveActiveProduct( v.xy ) : double2(0,0);
+    double2 v2_4 = tid.x <= 3 ? WaveActiveProduct( v.xy ) : double2(0,0);
+
+    double3 v3_1 = tid.x <= 0 ? WaveActiveProduct( v.xyz ) : double3(0,0,0);
+    double3 v3_2 = tid.x <= 1 ? WaveActiveProduct( v.xyz ) : double3(0,0,0);
+    double3 v3_3 = tid.x <= 2 ? WaveActiveProduct( v.xyz ) : double3(0,0,0);
+    double3 v3_4 = tid.x <= 3 ? WaveActiveProduct( v.xyz ) : double3(0,0,0);
+
+    double4 v4_1 = tid.x <= 0 ? WaveActiveProduct( v ) : double4(0,0,0,0);
+    double4 v4_2 = tid.x <= 1 ? WaveActiveProduct( v ) : double4(0,0,0,0);
+    double4 v4_3 = tid.x <= 2 ? WaveActiveProduct( v ) : double4(0,0,0,0);
+    double4 v4_4 = tid.x <= 3 ? WaveActiveProduct( v ) : double4(0,0,0,0);
+
+    double scalars[4] = { s1, s2, s3, s4 };
+    double2 vec2s [4] = { v2_1, v2_2, v2_3, v2_4 };
+    double3 vec3s [4] = { v3_1, v3_2, v3_3, v3_4 };
+    double4 vec4s [4] = { v4_1, v4_2, v4_3, v4_4 };
+
+
+    Out1[tid.x].x   = scalars[tid.x];
+    Out2[tid.x].xy  = vec2s[tid.x];
+    Out3[tid.x].xyz = vec3s[tid.x];
+    Out4[tid.x]     = vec4s[tid.x];
+
+    // constant folding case
+    Out5[0] = WaveActiveProduct(double4(1,2,3,4));
+}
+
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Float64
+    Stride: 32
+    Data: [1.0, 2.0, 4.0, 8.0]
+  - Name: Out1
+    Format: Float64
+    Stride: 32
+    FillSize: 32
+  - Name: Out2
+    Format: Float64
+    Stride: 32
+    FillSize: 32
+  - Name: Out3
+    Format: Float64
+    Stride: 32
+    FillSize: 32
+  - Name: Out4
+    Format: Float64
+    Stride: 32
+    FillSize: 32
+  - Name: Out5
+    Format: Float64
+    Stride: 32
+    FillSize: 8
+  - Name: ExpectedOut1
+    Format: Float64
+    Stride: 32
+    Data: [1.0, 0.0, 0.0, 0.0, 1.0, 0.0, 0.0, 0.0, 1.0, 0.0, 0.0, 0.0, 1.0, 0.0, 0.0, 0.0]
+  - Name: ExpectedOut2
+    Format: Float64
+    Stride: 32
+    Data: [1.0, 2.0, 0.0, 0.0, 1.0, 4.0, 0.0, 0.0, 1.0, 8.0, 0.0, 0.0, 1.0, 16.0, 0.0, 0.0]
+  - Name: ExpectedOut3
+    Format: Float64
+    Stride: 32
+    Data: [1.0, 2.0, 4.0, 0.0, 1.0, 4.0, 16.0, 0.0, 1.0, 8.0, 64.0, 0.0, 1.0, 16.0, 256.0, 0.0]
+  - Name: ExpectedOut4
+    Format: Float64
+    Stride: 32
+    Data: [1.0, 2.0, 4.0, 8.0, 1.0, 4.0, 16.0, 64.0, 1.0, 8.0, 64.0, 512.0, 1.0, 16.0, 256.0, 4096.0]
+  - Name: ExpectedOut5
+    Format: Float64
+    Stride: 32
+    Data: [1.0, 16.0, 81.0, 256.0]
+Results:
+  - Result: ExpectedOut1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: ExpectedOut2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: ExpectedOut3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: ExpectedOut4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: ExpectedOut5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+
+...
+#--- end
+
+# Bug https://github.com/llvm/llvm-project/issues/156775
+# XFAIL: Clang
+
+# Bug https://github.com/llvm/offload-test-suite/issues/393
+# XFAIL: Metal
+
+
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o
diff --git a/test/WaveOps/WaveActiveProduct.int16.test b/test/WaveOps/WaveActiveProduct.int16.test
new file mode 100644
index 000000000..94913fadd
--- /dev/null
+++ b/test/WaveOps/WaveActiveProduct.int16.test
@@ -0,0 +1,334 @@
+#--- source.hlsl
+// ints
+StructuredBuffer<int16_t4> In  : register(t0);
+RWStructuredBuffer<int16_t4> Out1 : register(u1);
+RWStructuredBuffer<int16_t4> Out2 : register(u2);
+RWStructuredBuffer<int16_t4> Out3 : register(u3);
+RWStructuredBuffer<int16_t4> Out4 : register(u4);
+RWStructuredBuffer<int16_t4> Out5 : register(u5);
+
+// uints
+StructuredBuffer<uint16_t4> UIn  : register(t6);
+RWStructuredBuffer<uint16_t4> UOut1 : register(u7);
+RWStructuredBuffer<uint16_t4> UOut2 : register(u8);
+RWStructuredBuffer<uint16_t4> UOut3 : register(u9);
+RWStructuredBuffer<uint16_t4> UOut4 : register(u10);
+RWStructuredBuffer<uint16_t4> UOut5 : register(u11);
+
+[numthreads(4,1,1)]
+void main(uint3 tid : SV_GroupThreadID)
+{
+    int16_t v = In[0];
+
+    // Mask per "active lane set": only <=N lanes contribute
+    int16_t s1 = tid.x <= 0 ? WaveActiveProduct( v.x ) : 0;
+    int16_t s2 = tid.x <= 1 ? WaveActiveProduct( v.x ) : 0;
+    int16_t s3 = tid.x <= 2 ? WaveActiveProduct( v.x ) : 0;
+    int16_t s4 = tid.x <= 3 ? WaveActiveProduct( v.x ) : 0;
+
+    int16_t2 v2_1 = tid.x <= 0 ? WaveActiveProduct( v.xy ) : int16_t2(0,0);
+    int16_t2 v2_2 = tid.x <= 1 ? WaveActiveProduct( v.xy ) : int16_t2(0,0);
+    int16_t2 v2_3 = tid.x <= 2 ? WaveActiveProduct( v.xy ) : int16_t2(0,0);
+    int16_t2 v2_4 = tid.x <= 3 ? WaveActiveProduct( v.xy ) : int16_t2(0,0);
+
+    int16_t3 v3_1 = tid.x <= 0 ? WaveActiveProduct( v.xyz ) : int16_t3(0,0,0);
+    int16_t3 v3_2 = tid.x <= 1 ? WaveActiveProduct( v.xyz ) : int16_t3(0,0,0);
+    int16_t3 v3_3 = tid.x <= 2 ? WaveActiveProduct( v.xyz ) : int16_t3(0,0,0);
+    int16_t3 v3_4 = tid.x <= 3 ? WaveActiveProduct( v.xyz ) : int16_t3(0,0,0);
+
+    int16_t4 v4_1 = tid.x <= 0 ? WaveActiveProduct( v ) : int16_t4(0,0,0,0);
+    int16_t4 v4_2 = tid.x <= 1 ? WaveActiveProduct( v ) : int16_t4(0,0,0,0);
+    int16_t4 v4_3 = tid.x <= 2 ? WaveActiveProduct( v ) : int16_t4(0,0,0,0);
+    int16_t4 v4_4 = tid.x <= 3 ? WaveActiveProduct( v ) : int16_t4(0,0,0,0);
+
+    int16_t scalars[4] = { s1, s2, s3, s4 };
+    int16_t2 vec2s [4] = { v2_1, v2_2, v2_3, v2_4 };
+    int16_t3 vec3s [4] = { v3_1, v3_2, v3_3, v3_4 };
+    int16_t4 vec4s [4] = { v4_1, v4_2, v4_3, v4_4 };
+
+    Out1[tid.x].x   = scalars[tid.x];
+    Out2[tid.x].xy  = vec2s[tid.x];
+    Out3[tid.x].xyz = vec3s[tid.x];
+    Out4[tid.x]     = vec4s[tid.x];
+
+    // constant folding case
+    Out5[0] = WaveActiveProduct(int16_t4(1,2,3,4));
+
+    // UINT case
+
+    uint16_t4 uv = UIn[0];
+
+    // Mask per "active lane set": only <=N lanes contribute
+    uint16_t us1 = tid.x <= 0 ? WaveActiveProduct( uv.x ) : 0;
+    uint16_t us2 = tid.x <= 1 ? WaveActiveProduct( uv.x ) : 0;
+    uint16_t us3 = tid.x <= 2 ? WaveActiveProduct( uv.x ) : 0;
+    uint16_t us4 = tid.x <= 3 ? WaveActiveProduct( uv.x ) : 0;
+
+    uint16_t2 uv2_1 = tid.x <= 0 ? WaveActiveProduct( uv.xy ) : uint16_t2(0,0);
+    uint16_t2 uv2_2 = tid.x <= 1 ? WaveActiveProduct( uv.xy ) : uint16_t2(0,0);
+    uint16_t2 uv2_3 = tid.x <= 2 ? WaveActiveProduct( uv.xy ) : uint16_t2(0,0);
+    uint16_t2 uv2_4 = tid.x <= 3 ? WaveActiveProduct( uv.xy ) : uint16_t2(0,0);
+
+    uint16_t3 uv3_1 = tid.x <= 0 ? WaveActiveProduct( uv.xyz ) : uint16_t3(0,0,0);
+    uint16_t3 uv3_2 = tid.x <= 1 ? WaveActiveProduct( uv.xyz ) : uint16_t3(0,0,0);
+    uint16_t3 uv3_3 = tid.x <= 2 ? WaveActiveProduct( uv.xyz ) : uint16_t3(0,0,0);
+    uint16_t3 uv3_4 = tid.x <= 3 ? WaveActiveProduct( uv.xyz ) : uint16_t3(0,0,0);
+
+    uint16_t4 uv4_1 = tid.x <= 0 ? WaveActiveProduct( uv ) : uint16_t4(0,0,0,0);
+    uint16_t4 uv4_2 = tid.x <= 1 ? WaveActiveProduct( uv ) : uint16_t4(0,0,0,0);
+    uint16_t4 uv4_3 = tid.x <= 2 ? WaveActiveProduct( uv ) : uint16_t4(0,0,0,0);
+    uint16_t4 uv4_4 = tid.x <= 3 ? WaveActiveProduct( uv ) : uint16_t4(0,0,0,0);
+
+    uint16_t uscalars[4] = { us1, us2, us3, us4 };
+    uint16_t2 uvec2s [4] = { uv2_1, uv2_2, uv2_3, uv2_4 };
+    uint16_t3 uvec3s [4] = { uv3_1, uv3_2, uv3_3, uv3_4 };
+    uint16_t4 uvec4s [4] = { uv4_1, uv4_2, uv4_3, uv4_4 };
+
+    UOut1[tid.x].x   = uscalars[tid.x];
+    UOut2[tid.x].xy  = uvec2s[tid.x];
+    UOut3[tid.x].xyz = uvec3s[tid.x];
+    UOut4[tid.x]     = uvec4s[tid.x];
+
+    // constant folding case
+    UOut5[0] = WaveActiveProduct(uint16_t4(1,2,3,4));
+}
+
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Int16
+    Stride: 8
+    Data: [1, 2, 4, 8]
+  - Name: Out1
+    Format: Int16
+    Stride: 8
+    FillSize: 32
+  - Name: Out2
+    Format: Int16
+    Stride: 8
+    FillSize: 32
+  - Name: Out3
+    Format: Int16
+    Stride: 8
+    FillSize: 32
+  - Name: Out4
+    Format: Int16
+    Stride: 8
+    FillSize: 32
+  - Name: Out5
+    Format: Int16
+    Stride: 8
+    FillSize: 8
+  - Name: ExpectedOut1
+    Format: Int16
+    Stride: 8
+    Data: [1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0]
+  - Name: ExpectedOut2
+    Format: Int16
+    Stride: 8
+    Data: [1, 2, 0, 0, 1, 4, 0, 0, 1, 8, 0, 0, 1, 16, 0, 0]
+  - Name: ExpectedOut3
+    Format: Int16
+    Stride: 8
+    Data: [1, 2, 4, 0, 1, 4, 16, 0, 1, 8, 64, 0, 1, 16, 256, 0]
+  - Name: ExpectedOut4
+    Format: Int16
+    Stride: 8
+    Data: [1, 2, 4, 8, 1, 4, 16, 64, 1, 8, 64, 512, 1, 16, 256, 4096]
+  - Name: ExpectedOut5
+    Format: Int16
+    Stride: 8
+    Data: [1, 16, 81, 256]
+  - Name: UIn
+    Format: Int16
+    Stride: 8
+    Data: [1, 2, 4, 8]
+  - Name: UOut1
+    Format: Int16
+    Stride: 8
+    FillSize: 32
+  - Name: UOut2
+    Format: Int16
+    Stride: 8
+    FillSize: 32
+  - Name: UOut3
+    Format: Int16
+    Stride: 8
+    FillSize: 32
+  - Name: UOut4
+    Format: Int16
+    Stride: 8
+    FillSize: 32
+  - Name: UOut5
+    Format: Int16
+    Stride: 8
+    FillSize: 8
+  - Name: UExpectedOut1
+    Format: Int16
+    Stride: 8
+    Data: [1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0]
+  - Name: UExpectedOut2
+    Format: Int16
+    Stride: 8
+    Data: [1, 2, 0, 0, 1, 4, 0, 0, 1, 8, 0, 0, 1, 16, 0, 0]
+  - Name: UExpectedOut3
+    Format: Int16
+    Stride: 8
+    Data: [1, 2, 4, 0, 1, 4, 16, 0, 1, 8, 64, 0, 1, 16, 256, 0]
+  - Name: UExpectedOut4
+    Format: Int16
+    Stride: 8
+    Data: [1, 2, 4, 8, 1, 4, 16, 64, 1, 8, 64, 512, 1, 16, 256, 4096]
+  - Name: UExpectedOut5
+    Format: Int16
+    Stride: 8
+    Data: [1, 16, 81, 256]
+Results:
+  - Result: ExpectedOut1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: ExpectedOut2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: ExpectedOut3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: ExpectedOut4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: ExpectedOut5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+  - Result: UExpectedOut1
+    Rule: BufferExact
+    Actual: UOut1
+    Expected: UExpectedOut1
+  - Result: UExpectedOut2
+    Rule: BufferExact
+    Actual: UOut2
+    Expected: UExpectedOut2
+  - Result: UExpectedOut3
+    Rule: BufferExact
+    Actual: UOut3
+    Expected: UExpectedOut3
+  - Result: UExpectedOut4
+    Rule: BufferExact
+    Actual: UOut4
+    Expected: UExpectedOut4
+  - Result: UExpectedOut5
+    Rule: BufferExact
+    Actual: UOut5
+    Expected: UExpectedOut5
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+    - Name: UIn
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 6
+        Space: 0
+      VulkanBinding:
+        Binding: 6
+    - Name: UOut1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 7
+        Space: 0
+      VulkanBinding:
+        Binding: 7
+    - Name: UOut2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 8
+        Space: 0
+      VulkanBinding:
+        Binding: 8
+    - Name: UOut3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 9
+        Space: 0
+      VulkanBinding:
+        Binding: 9
+    - Name: UOut4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 10
+        Space: 0
+      VulkanBinding:
+        Binding: 10
+    - Name: UOut5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 11
+        Space: 0
+      VulkanBinding:
+        Binding: 11
+
+...
+#--- end
+
+# REQUIRES: Int16
+
+# Bug https://github.com/llvm/llvm-project/issues/156775
+# XFAIL: Clang
+
+# Bug https://github.com/llvm/offload-test-suite/issues/393
+# XFAIL: Metal
+
+# RUN: split-file %s %t
+# RUN: %dxc_target-enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o
diff --git a/test/WaveOps/WaveActiveProduct.int32.test b/test/WaveOps/WaveActiveProduct.int32.test
new file mode 100644
index 000000000..d9091144c
--- /dev/null
+++ b/test/WaveOps/WaveActiveProduct.int32.test
@@ -0,0 +1,334 @@
+#--- source.hlsl
+// ints
+StructuredBuffer<int4> In  : register(t0);
+RWStructuredBuffer<int4> Out1 : register(u1);
+RWStructuredBuffer<int4> Out2 : register(u2);
+RWStructuredBuffer<int4> Out3 : register(u3);
+RWStructuredBuffer<int4> Out4 : register(u4);
+RWStructuredBuffer<int4> Out5 : register(u5);
+
+// uints
+StructuredBuffer<uint4> UIn  : register(t6);
+RWStructuredBuffer<uint4> UOut1 : register(u7);
+RWStructuredBuffer<uint4> UOut2 : register(u8);
+RWStructuredBuffer<uint4> UOut3 : register(u9);
+RWStructuredBuffer<uint4> UOut4 : register(u10);
+RWStructuredBuffer<uint4> UOut5 : register(u11);
+
+[numthreads(4,1,1)]
+void main(uint3 tid : SV_GroupThreadID)
+{
+    int v = In[0];
+
+    // Mask per "active lane set": only <=N lanes contribute
+    int s1 = tid.x <= 0 ? WaveActiveProduct( v.x ) : 0;
+    int s2 = tid.x <= 1 ? WaveActiveProduct( v.x ) : 0;
+    int s3 = tid.x <= 2 ? WaveActiveProduct( v.x ) : 0;
+    int s4 = tid.x <= 3 ? WaveActiveProduct( v.x ) : 0;
+
+    int2 v2_1 = tid.x <= 0 ? WaveActiveProduct( v.xy ) : int2(0,0);
+    int2 v2_2 = tid.x <= 1 ? WaveActiveProduct( v.xy ) : int2(0,0);
+    int2 v2_3 = tid.x <= 2 ? WaveActiveProduct( v.xy ) : int2(0,0);
+    int2 v2_4 = tid.x <= 3 ? WaveActiveProduct( v.xy ) : int2(0,0);
+
+    int3 v3_1 = tid.x <= 0 ? WaveActiveProduct( v.xyz ) : int3(0,0,0);
+    int3 v3_2 = tid.x <= 1 ? WaveActiveProduct( v.xyz ) : int3(0,0,0);
+    int3 v3_3 = tid.x <= 2 ? WaveActiveProduct( v.xyz ) : int3(0,0,0);
+    int3 v3_4 = tid.x <= 3 ? WaveActiveProduct( v.xyz ) : int3(0,0,0);
+
+    int4 v4_1 = tid.x <= 0 ? WaveActiveProduct( v ) : int4(0,0,0,0);
+    int4 v4_2 = tid.x <= 1 ? WaveActiveProduct( v ) : int4(0,0,0,0);
+    int4 v4_3 = tid.x <= 2 ? WaveActiveProduct( v ) : int4(0,0,0,0);
+    int4 v4_4 = tid.x <= 3 ? WaveActiveProduct( v ) : int4(0,0,0,0);
+
+    int scalars[4] = { s1, s2, s3, s4 };
+    int2 vec2s [4] = { v2_1, v2_2, v2_3, v2_4 };
+    int3 vec3s [4] = { v3_1, v3_2, v3_3, v3_4 };
+    int4 vec4s [4] = { v4_1, v4_2, v4_3, v4_4 };
+
+    Out1[tid.x].x   = scalars[tid.x];
+    Out2[tid.x].xy  = vec2s[tid.x];
+    Out3[tid.x].xyz = vec3s[tid.x];
+    Out4[tid.x]     = vec4s[tid.x];
+
+    // constant folding case
+    Out5[0] = WaveActiveProduct(int4(1,2,3,4));
+
+    // UINT case
+
+    uint4 uv = UIn[0];
+
+    // Mask per "active lane set": only <=N lanes contribute
+    uint us1 = tid.x <= 0 ? WaveActiveProduct( uv.x ) : 0;
+    uint us2 = tid.x <= 1 ? WaveActiveProduct( uv.x ) : 0;
+    uint us3 = tid.x <= 2 ? WaveActiveProduct( uv.x ) : 0;
+    uint us4 = tid.x <= 3 ? WaveActiveProduct( uv.x ) : 0;
+
+    uint2 uv2_1 = tid.x <= 0 ? WaveActiveProduct( uv.xy ) : uint2(0,0);
+    uint2 uv2_2 = tid.x <= 1 ? WaveActiveProduct( uv.xy ) : uint2(0,0);
+    uint2 uv2_3 = tid.x <= 2 ? WaveActiveProduct( uv.xy ) : uint2(0,0);
+    uint2 uv2_4 = tid.x <= 3 ? WaveActiveProduct( uv.xy ) : uint2(0,0);
+
+    uint3 uv3_1 = tid.x <= 0 ? WaveActiveProduct( uv.xyz ) : uint3(0,0,0);
+    uint3 uv3_2 = tid.x <= 1 ? WaveActiveProduct( uv.xyz ) : uint3(0,0,0);
+    uint3 uv3_3 = tid.x <= 2 ? WaveActiveProduct( uv.xyz ) : uint3(0,0,0);
+    uint3 uv3_4 = tid.x <= 3 ? WaveActiveProduct( uv.xyz ) : uint3(0,0,0);
+
+    uint4 uv4_1 = tid.x <= 0 ? WaveActiveProduct( uv ) : uint4(0,0,0,0);
+    uint4 uv4_2 = tid.x <= 1 ? WaveActiveProduct( uv ) : uint4(0,0,0,0);
+    uint4 uv4_3 = tid.x <= 2 ? WaveActiveProduct( uv ) : uint4(0,0,0,0);
+    uint4 uv4_4 = tid.x <= 3 ? WaveActiveProduct( uv ) : uint4(0,0,0,0);
+
+    uint uscalars[4] = { us1, us2, us3, us4 };
+    uint2 uvec2s [4] = { uv2_1, uv2_2, uv2_3, uv2_4 };
+    uint3 uvec3s [4] = { uv3_1, uv3_2, uv3_3, uv3_4 };
+    uint4 uvec4s [4] = { uv4_1, uv4_2, uv4_3, uv4_4 };
+
+    UOut1[tid.x].x   = uscalars[tid.x];
+    UOut2[tid.x].xy  = uvec2s[tid.x];
+    UOut3[tid.x].xyz = uvec3s[tid.x];
+    UOut4[tid.x]     = uvec4s[tid.x];
+
+    // constant folding case
+    UOut5[0] = WaveActiveProduct(uint4(1,2,3,4));
+}
+
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Int32
+    Stride: 16
+    Data: [1, 2, 4, 8]
+  - Name: Out1
+    Format: Int32
+    Stride: 16
+    FillSize: 32
+  - Name: Out2
+    Format: Int32
+    Stride: 16
+    FillSize: 32
+  - Name: Out3
+    Format: Int32
+    Stride: 16
+    FillSize: 32
+  - Name: Out4
+    Format: Int32
+    Stride: 16
+    FillSize: 32
+  - Name: Out5
+    Format: Int32
+    Stride: 16
+    FillSize: 8
+  - Name: ExpectedOut1
+    Format: Int32
+    Stride: 16
+    Data: [1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0]
+  - Name: ExpectedOut2
+    Format: Int32
+    Stride: 16
+    Data: [1, 2, 0, 0, 1, 4, 0, 0, 1, 8, 0, 0, 1, 16, 0, 0]
+  - Name: ExpectedOut3
+    Format: Int32
+    Stride: 16
+    Data: [1, 2, 4, 0, 1, 4, 16, 0, 1, 8, 64, 0, 1, 16, 256, 0]
+  - Name: ExpectedOut4
+    Format: Int32
+    Stride: 16
+    Data: [1, 2, 4, 8, 1, 4, 16, 64, 1, 8, 64, 512, 1, 16, 256, 4096]
+  - Name: ExpectedOut5
+    Format: Int32
+    Stride: 16
+    Data: [1, 16, 81, 256]
+  - Name: UIn
+    Format: Int32
+    Stride: 16
+    Data: [1, 2, 4, 8]
+  - Name: UOut1
+    Format: Int32
+    Stride: 16
+    FillSize: 32
+  - Name: UOut2
+    Format: Int32
+    Stride: 16
+    FillSize: 32
+  - Name: UOut3
+    Format: Int32
+    Stride: 16
+    FillSize: 32
+  - Name: UOut4
+    Format: Int32
+    Stride: 16
+    FillSize: 32
+  - Name: UOut5
+    Format: Int32
+    Stride: 16
+    FillSize: 8
+  - Name: UExpectedOut1
+    Format: Int32
+    Stride: 16
+    Data: [1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0]
+  - Name: UExpectedOut2
+    Format: Int32
+    Stride: 16
+    Data: [1, 2, 0, 0, 1, 4, 0, 0, 1, 8, 0, 0, 1, 16, 0, 0]
+  - Name: UExpectedOut3
+    Format: Int32
+    Stride: 16
+    Data: [1, 2, 4, 0, 1, 4, 16, 0, 1, 8, 64, 0, 1, 16, 256, 0]
+  - Name: UExpectedOut4
+    Format: Int32
+    Stride: 16
+    Data: [1, 2, 4, 8, 1, 4, 16, 64, 1, 8, 64, 512, 1, 16, 256, 4096]
+  - Name: UExpectedOut5
+    Format: Int32
+    Stride: 16
+    Data: [1, 16, 81, 256]
+Results:
+  - Result: ExpectedOut1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: ExpectedOut2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: ExpectedOut3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: ExpectedOut4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: ExpectedOut5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+  - Result: UExpectedOut1
+    Rule: BufferExact
+    Actual: UOut1
+    Expected: UExpectedOut1
+  - Result: UExpectedOut2
+    Rule: BufferExact
+    Actual: UOut2
+    Expected: UExpectedOut2
+  - Result: UExpectedOut3
+    Rule: BufferExact
+    Actual: UOut3
+    Expected: UExpectedOut3
+  - Result: UExpectedOut4
+    Rule: BufferExact
+    Actual: UOut4
+    Expected: UExpectedOut4
+  - Result: UExpectedOut5
+    Rule: BufferExact
+    Actual: UOut5
+    Expected: UExpectedOut5
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+    - Name: UIn
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 6
+        Space: 0
+      VulkanBinding:
+        Binding: 6
+    - Name: UOut1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 7
+        Space: 0
+      VulkanBinding:
+        Binding: 7
+    - Name: UOut2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 8
+        Space: 0
+      VulkanBinding:
+        Binding: 8
+    - Name: UOut3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 9
+        Space: 0
+      VulkanBinding:
+        Binding: 9
+    - Name: UOut4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 10
+        Space: 0
+      VulkanBinding:
+        Binding: 10
+    - Name: UOut5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 11
+        Space: 0
+      VulkanBinding:
+        Binding: 11
+
+...
+#--- end
+
+
+
+# Bug https://github.com/llvm/llvm-project/issues/156775
+# XFAIL: Clang
+
+# Bug https://github.com/llvm/offload-test-suite/issues/393
+# XFAIL: Metal
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o
\ No newline at end of file
diff --git a/test/WaveOps/WaveActiveProduct.int64.test b/test/WaveOps/WaveActiveProduct.int64.test
new file mode 100644
index 000000000..c5f1cc35c
--- /dev/null
+++ b/test/WaveOps/WaveActiveProduct.int64.test
@@ -0,0 +1,335 @@
+#--- source.hlsl
+// ints
+StructuredBuffer<int64_t4> In  : register(t0);
+RWStructuredBuffer<int64_t4> Out1 : register(u1);
+RWStructuredBuffer<int64_t4> Out2 : register(u2);
+RWStructuredBuffer<int64_t4> Out3 : register(u3);
+RWStructuredBuffer<int64_t4> Out4 : register(u4);
+RWStructuredBuffer<int64_t4> Out5 : register(u5);
+
+// uints
+StructuredBuffer<uint64_t4> UIn  : register(t6);
+RWStructuredBuffer<uint64_t4> UOut1 : register(u7);
+RWStructuredBuffer<uint64_t4> UOut2 : register(u8);
+RWStructuredBuffer<uint64_t4> UOut3 : register(u9);
+RWStructuredBuffer<uint64_t4> UOut4 : register(u10);
+RWStructuredBuffer<uint64_t4> UOut5 : register(u11);
+
+[numthreads(4,1,1)]
+void main(uint3 tid : SV_GroupThreadID)
+{
+    int64_t v = In[0];
+
+    // Mask per "active lane set": only <=N lanes contribute
+    int64_t s1 = tid.x <= 0 ? WaveActiveProduct( v.x ) : 0;
+    int64_t s2 = tid.x <= 1 ? WaveActiveProduct( v.x ) : 0;
+    int64_t s3 = tid.x <= 2 ? WaveActiveProduct( v.x ) : 0;
+    int64_t s4 = tid.x <= 3 ? WaveActiveProduct( v.x ) : 0;
+
+    int64_t2 v2_1 = tid.x <= 0 ? WaveActiveProduct( v.xy ) : int64_t2(0,0);
+    int64_t2 v2_2 = tid.x <= 1 ? WaveActiveProduct( v.xy ) : int64_t2(0,0);
+    int64_t2 v2_3 = tid.x <= 2 ? WaveActiveProduct( v.xy ) : int64_t2(0,0);
+    int64_t2 v2_4 = tid.x <= 3 ? WaveActiveProduct( v.xy ) : int64_t2(0,0);
+
+    int64_t3 v3_1 = tid.x <= 0 ? WaveActiveProduct( v.xyz ) : int64_t3(0,0,0);
+    int64_t3 v3_2 = tid.x <= 1 ? WaveActiveProduct( v.xyz ) : int64_t3(0,0,0);
+    int64_t3 v3_3 = tid.x <= 2 ? WaveActiveProduct( v.xyz ) : int64_t3(0,0,0);
+    int64_t3 v3_4 = tid.x <= 3 ? WaveActiveProduct( v.xyz ) : int64_t3(0,0,0);
+
+    int64_t4 v4_1 = tid.x <= 0 ? WaveActiveProduct( v ) : int64_t4(0,0,0,0);
+    int64_t4 v4_2 = tid.x <= 1 ? WaveActiveProduct( v ) : int64_t4(0,0,0,0);
+    int64_t4 v4_3 = tid.x <= 2 ? WaveActiveProduct( v ) : int64_t4(0,0,0,0);
+    int64_t4 v4_4 = tid.x <= 3 ? WaveActiveProduct( v ) : int64_t4(0,0,0,0);
+
+    int64_t scalars[4] = { s1, s2, s3, s4 };
+    int64_t2 vec2s [4] = { v2_1, v2_2, v2_3, v2_4 };
+    int64_t3 vec3s [4] = { v3_1, v3_2, v3_3, v3_4 };
+    int64_t4 vec4s [4] = { v4_1, v4_2, v4_3, v4_4 };
+
+    Out1[tid.x].x   = scalars[tid.x];
+    Out2[tid.x].xy  = vec2s[tid.x];
+    Out3[tid.x].xyz = vec3s[tid.x];
+    Out4[tid.x]     = vec4s[tid.x];
+
+    // constant folding case
+    Out5[0] = WaveActiveProduct(int64_t4(1,2,3,4));
+
+    // UINT case
+
+    uint64_t4 uv = UIn[0];
+
+    // Mask per "active lane set": only <=N lanes contribute
+    uint64_t us1 = tid.x <= 0 ? WaveActiveProduct( uv.x ) : 0;
+    uint64_t us2 = tid.x <= 1 ? WaveActiveProduct( uv.x ) : 0;
+    uint64_t us3 = tid.x <= 2 ? WaveActiveProduct( uv.x ) : 0;
+    uint64_t us4 = tid.x <= 3 ? WaveActiveProduct( uv.x ) : 0;
+
+    uint64_t2 uv2_1 = tid.x <= 0 ? WaveActiveProduct( uv.xy ) : uint64_t2(0,0);
+    uint64_t2 uv2_2 = tid.x <= 1 ? WaveActiveProduct( uv.xy ) : uint64_t2(0,0);
+    uint64_t2 uv2_3 = tid.x <= 2 ? WaveActiveProduct( uv.xy ) : uint64_t2(0,0);
+    uint64_t2 uv2_4 = tid.x <= 3 ? WaveActiveProduct( uv.xy ) : uint64_t2(0,0);
+
+    uint64_t3 uv3_1 = tid.x <= 0 ? WaveActiveProduct( uv.xyz ) : uint64_t3(0,0,0);
+    uint64_t3 uv3_2 = tid.x <= 1 ? WaveActiveProduct( uv.xyz ) : uint64_t3(0,0,0);
+    uint64_t3 uv3_3 = tid.x <= 2 ? WaveActiveProduct( uv.xyz ) : uint64_t3(0,0,0);
+    uint64_t3 uv3_4 = tid.x <= 3 ? WaveActiveProduct( uv.xyz ) : uint64_t3(0,0,0);
+
+    uint64_t4 uv4_1 = tid.x <= 0 ? WaveActiveProduct( uv ) : uint64_t4(0,0,0,0);
+    uint64_t4 uv4_2 = tid.x <= 1 ? WaveActiveProduct( uv ) : uint64_t4(0,0,0,0);
+    uint64_t4 uv4_3 = tid.x <= 2 ? WaveActiveProduct( uv ) : uint64_t4(0,0,0,0);
+    uint64_t4 uv4_4 = tid.x <= 3 ? WaveActiveProduct( uv ) : uint64_t4(0,0,0,0);
+
+    uint64_t uscalars[4] = { us1, us2, us3, us4 };
+    uint64_t2 uvec2s [4] = { uv2_1, uv2_2, uv2_3, uv2_4 };
+    uint64_t3 uvec3s [4] = { uv3_1, uv3_2, uv3_3, uv3_4 };
+    uint64_t4 uvec4s [4] = { uv4_1, uv4_2, uv4_3, uv4_4 };
+
+    UOut1[tid.x].x   = uscalars[tid.x];
+    UOut2[tid.x].xy  = uvec2s[tid.x];
+    UOut3[tid.x].xyz = uvec3s[tid.x];
+    UOut4[tid.x]     = uvec4s[tid.x];
+
+    // constant folding case
+    UOut5[0] = WaveActiveProduct(uint64_t4(1,2,3,4));
+}
+
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Int64
+    Stride: 32
+    Data: [1, 2, 4, 8]
+  - Name: Out1
+    Format: Int64
+    Stride: 32
+    FillSize: 32
+  - Name: Out2
+    Format: Int64
+    Stride: 32
+    FillSize: 32
+  - Name: Out3
+    Format: Int64
+    Stride: 32
+    FillSize: 32
+  - Name: Out4
+    Format: Int64
+    Stride: 32
+    FillSize: 32
+  - Name: Out5
+    Format: Int64
+    Stride: 32
+    FillSize: 8
+  - Name: ExpectedOut1
+    Format: Int64
+    Stride: 32
+    Data: [1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0]
+  - Name: ExpectedOut2
+    Format: Int64
+    Stride: 32
+    Data: [1, 2, 0, 0, 1, 4, 0, 0, 1, 8, 0, 0, 1, 16, 0, 0]
+  - Name: ExpectedOut3
+    Format: Int64
+    Stride: 32
+    Data: [1, 2, 4, 0, 1, 4, 16, 0, 1, 8, 64, 0, 1, 16, 256, 0]
+  - Name: ExpectedOut4
+    Format: Int64
+    Stride: 32
+    Data: [1, 2, 4, 8, 1, 4, 16, 64, 1, 8, 64, 512, 1, 16, 256, 4096]
+  - Name: ExpectedOut5
+    Format: Int64
+    Stride: 32
+    Data: [1, 16, 81, 256]
+  - Name: UIn
+    Format: Int64
+    Stride: 32
+    Data: [1, 2, 4, 8]
+  - Name: UOut1
+    Format: Int64
+    Stride: 32
+    FillSize: 32
+  - Name: UOut2
+    Format: Int64
+    Stride: 32
+    FillSize: 32
+  - Name: UOut3
+    Format: Int64
+    Stride: 32
+    FillSize: 32
+  - Name: UOut4
+    Format: Int64
+    Stride: 32
+    FillSize: 32
+  - Name: UOut5
+    Format: Int64
+    Stride: 32
+    FillSize: 8
+  - Name: UExpectedOut1
+    Format: Int64
+    Stride: 32
+    Data: [1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0]
+  - Name: UExpectedOut2
+    Format: Int64
+    Stride: 32
+    Data: [1, 2, 0, 0, 1, 4, 0, 0, 1, 8, 0, 0, 1, 16, 0, 0]
+  - Name: UExpectedOut3
+    Format: Int64
+    Stride: 32
+    Data: [1, 2, 4, 0, 1, 4, 16, 0, 1, 8, 64, 0, 1, 16, 256, 0]
+  - Name: UExpectedOut4
+    Format: Int64
+    Stride: 32
+    Data: [1, 2, 4, 8, 1, 4, 16, 64, 1, 8, 64, 512, 1, 16, 256, 4096]
+  - Name: UExpectedOut5
+    Format: Int64
+    Stride: 32
+    Data: [1, 16, 81, 256]
+Results:
+  - Result: ExpectedOut1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: ExpectedOut2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: ExpectedOut3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: ExpectedOut4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: ExpectedOut5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+  - Result: UExpectedOut1
+    Rule: BufferExact
+    Actual: UOut1
+    Expected: UExpectedOut1
+  - Result: UExpectedOut2
+    Rule: BufferExact
+    Actual: UOut2
+    Expected: UExpectedOut2
+  - Result: UExpectedOut3
+    Rule: BufferExact
+    Actual: UOut3
+    Expected: UExpectedOut3
+  - Result: UExpectedOut4
+    Rule: BufferExact
+    Actual: UOut4
+    Expected: UExpectedOut4
+  - Result: UExpectedOut5
+    Rule: BufferExact
+    Actual: UOut5
+    Expected: UExpectedOut5
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+    - Name: UIn
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 6
+        Space: 0
+      VulkanBinding:
+        Binding: 6
+    - Name: UOut1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 7
+        Space: 0
+      VulkanBinding:
+        Binding: 7
+    - Name: UOut2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 8
+        Space: 0
+      VulkanBinding:
+        Binding: 8
+    - Name: UOut3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 9
+        Space: 0
+      VulkanBinding:
+        Binding: 9
+    - Name: UOut4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 10
+        Space: 0
+      VulkanBinding:
+        Binding: 10
+    - Name: UOut5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 11
+        Space: 0
+      VulkanBinding:
+        Binding: 11
+
+...
+#--- end
+
+
+
+# Bug https://github.com/llvm/llvm-project/issues/156775
+# XFAIL: Clang
+
+# Bug https://github.com/llvm/offload-test-suite/issues/393
+# XFAIL: Metal
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o
+
diff --git a/test/WaveOps/WaveActiveProduct.test b/test/WaveOps/WaveActiveProduct.test
new file mode 100644
index 000000000..d4ac11971
--- /dev/null
+++ b/test/WaveOps/WaveActiveProduct.test
@@ -0,0 +1,45 @@
+#--- source.hlsl
+RWBuffer<int> value;
+
+[numthreads(4, 1, 1)]
+void main(uint3 threadID : SV_DispatchThreadID) {
+  uint sum = 0;
+  switch (value[threadID.x]) {
+    case 0:
+      sum += WaveActiveProduct(2);
+      break;
+    default:
+      break;
+  }
+  sum += WaveActiveProduct(10);
+  value[threadID.x] = sum;
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: value
+    Format: Int32
+    Data: [ 0, 0, 1, 2]
+DescriptorSets:
+  - Resources:
+    - Name: value
+      Kind: RWBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+...
+#--- end
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_0 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o | FileCheck %s
+
+# CHECK: Data: [ 10004, 10004, 10000, 10000 ]