Hardware / Logical / HDL Design Daigram

[MichalMKsiazek]

Proposal

I am a massive fan of tools such as mermaid and plantuml (especially as a meotodoloy for project planning). However, I find that their focuse thends to be on software development and rightfully that is their popualr use case. I would love to see the functionality be exapnded for Logical Hardware diagrams.

The diagram should have:

• Logical Operators
• Module Blocks
  • abstractions of an existing collection of logical elemets with inpuyts and ouputs
• Arrmows to represent single signal connections
• Arrows to represent multi singal connections (mabey with with representing number of singals)
• Element to represent a BUS
• Elements to represent inputs and outputs for particual compoents

Use Cases

RTL, HDL enginnering and design for FPGAs and ASIC Architectures at the conceptual deisgn stage.

The representation of Hardware designs in existing tools that integrade Mermaid e.g. GitHub

Screenshots

Example logical operators

Example of Existing daigrams (Quartus)

Example of a logical and block daigram mix

Example of me abusing the class diagram system to help accomplish someting simillar

Example of a BUS (Again abusing the Class Diagram Style)

The bus is the verical line and should help organised common connectiosn between mulitple blocks. I think this looks more organised then the above diagram.

Syntax

Taking the example from the "Example of a logical and block daigram mix" of the ALU

HardwareDiagram

  val3 = val1 + val2 %% this would generate an AND gate
  val3 = val1 | val2 %% this would generate an OR gate
  val3 = mux_val ? val1 : val2 %% this would generate a multiplexer symbol (e.g. A Mux / B Mux)
  ...

  module ALU{
    inputclk clk_i : wire %% closcks hsould probobaly have a unique 'type' to allow for special symbol to be added to the block
    input a_i : wire[0..7]
    input  b_i : wire[0..7]
    output q_o : wire[0..7]
    output EQ : wire
    output LT : wire
    output LTU : wire
    inout some_input_and_output_value %% port that would be both input and output therfore have a bi-directional arrow
    interface axi4_lite : axi4_lite.master %% Note the .master defines the subtype (a.k.a. modports) in this case the master end of a master and slave interface topology.

Implementation

None