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system(L4) update STM32L4xx HAL Drivers to v1.13.3
Included in STM32CubeL4 FW v1.17.2 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent e0c2e45 commit 73e67e8

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‎system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h‎

Lines changed: 93 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,12 @@ extern "C" {
104104
#if defined(STM32H7)
105105
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
106106
#endif /* STM32H7 */
107+
108+
#if defined(STM32U5)
109+
#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
110+
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
111+
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
112+
#endif /* STM32U5 */
107113
/**
108114
* @}
109115
*/
@@ -227,6 +233,7 @@ extern "C" {
227233
*/
228234
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
229235
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
236+
230237
/**
231238
* @}
232239
*/
@@ -410,6 +417,10 @@ extern "C" {
410417
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
411418

412419
#endif /* STM32H7 */
420+
421+
#if defined(STM32U5)
422+
#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
423+
#endif /* STM32U5 */
413424
/**
414425
* @}
415426
*/
@@ -657,6 +668,10 @@ extern "C" {
657668
#if defined(STM32U5)
658669
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
659670
#endif /* STM32U5 */
671+
#if defined(STM32U5)
672+
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
673+
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
674+
#endif /* STM32U5 */
660675
/**
661676
* @}
662677
*/
@@ -1690,6 +1705,79 @@ extern "C" {
16901705

16911706
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
16921707

1708+
#if defined (STM32U5)
1709+
#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
1710+
#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
1711+
#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
1712+
#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
1713+
#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
1714+
#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
1715+
#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
1716+
#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
1717+
#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
1718+
#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
1719+
#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
1720+
#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
1721+
#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
1722+
1723+
#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
1724+
#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
1725+
#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
1726+
1727+
#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
1728+
#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
1729+
#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
1730+
#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
1731+
#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
1732+
#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
1733+
#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
1734+
#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
1735+
#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
1736+
#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
1737+
#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
1738+
#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
1739+
#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
1740+
#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
1741+
1742+
#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
1743+
1744+
#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
1745+
#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
1746+
#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
1747+
#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
1748+
#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
1749+
#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
1750+
#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
1751+
#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
1752+
#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
1753+
#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
1754+
#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
1755+
#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
1756+
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
1757+
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
1758+
1759+
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
1760+
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
1761+
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
1762+
#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
1763+
#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
1764+
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
1765+
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
1766+
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
1767+
1768+
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
1769+
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
1770+
#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
1771+
1772+
#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
1773+
#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
1774+
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
1775+
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
1776+
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
1777+
1778+
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
1779+
#endif
1780+
16931781
/**
16941782
* @}
16951783
*/
@@ -3458,7 +3546,10 @@ extern "C" {
34583546
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
34593547
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
34603548
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3461-
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3549+
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3550+
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
3551+
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
3552+
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
34623553
#endif
34633554

34643555
/**
@@ -3541,7 +3632,7 @@ extern "C" {
35413632
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
35423633
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
35433634

3544-
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
3635+
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
35453636
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
35463637
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
35473638
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE

‎system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h‎

Lines changed: 29 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -102,21 +102,25 @@ typedef struct
102102
{
103103
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
104104
configuration, first one for a 16-bit configuration).
105-
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
105+
This parameter must be a number between
106+
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
106107

107108
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
108109
configuration, second one for a 16-bit configuration).
109-
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
110+
This parameter must be a number between
111+
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
110112

111113
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
112114
according to the mode (MSBs for a 32-bit configuration,
113115
first one for a 16-bit configuration).
114-
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
116+
This parameter must be a number between
117+
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
115118

116119
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
117120
according to the mode (LSBs for a 32-bit configuration,
118121
second one for a 16-bit configuration).
119-
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
122+
This parameter must be a number between
123+
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
120124

121125
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
122126
This parameter can be a value of @ref CAN_filter_FIFO */
@@ -294,11 +298,11 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to
294298
#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
295299
#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
296300
#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
297-
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
301+
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
298302
#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */
299-
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
303+
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
300304
#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */
301-
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
305+
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
302306
#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
303307
#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
304308
#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
@@ -329,7 +333,8 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to
329333
#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
330334
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
331335
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
332-
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
336+
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with
337+
silent mode */
333338
/**
334339
* @}
335340
*/
@@ -644,7 +649,8 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
644649

645650
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
646651
/* Callbacks Register/UnRegister functions ***********************************/
647-
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));
652+
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID,
653+
void (* pCallback)(CAN_HandleTypeDef *_hcan));
648654
HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
649655

650656
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
@@ -658,7 +664,7 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca
658664
*/
659665

660666
/* Configuration functions ****************************************************/
661-
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
667+
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig);
662668

663669
/**
664670
* @}
@@ -674,14 +680,16 @@ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
674680
HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
675681
HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
676682
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
677-
uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
678-
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
683+
uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan);
684+
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
685+
const uint8_t aData[], uint32_t *pTxMailbox);
679686
HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
680-
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
681-
uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
682-
uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
683-
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
684-
uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
687+
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan);
688+
uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
689+
uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
690+
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
691+
CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
692+
uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo);
685693

686694
/**
687695
* @}
@@ -729,8 +737,8 @@ void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
729737
* @{
730738
*/
731739
/* Peripheral State and Error functions ***************************************/
732-
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
733-
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
740+
HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan);
741+
uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan);
734742
HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
735743

736744
/**
@@ -808,7 +816,8 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
808816
#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
809817
((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
810818
((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
811-
#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
819+
#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | \
820+
CAN_TX_MAILBOX2))
812821
#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
813822
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
814823
#define IS_CAN_DLC(DLC) ((DLC) <= 8U)

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