Verilog Code Cheat Sheet for Computer Architecture Modules

This repository serves as a comprehensive cheat sheet for various Verilog modules related to Computer Organization and Architecture (COA). It provides ready-to-use Verilog code snippets for different components, facilitating quick reference and implementation.

Table of Contents

• Overview
• Available Verilog Codes
• Accessing the Cheat Sheet
• Usage Instructions
• Contributing
• License

Overview

The primary objective of this repository is to offer a centralized collection of Verilog code snippets for essential computer architecture modules. Each module is presented in a concise format, allowing for easy copying and integration into your projects.

Available Verilog Codes

The repository includes Verilog codes for the following modules:

• Arithmetic Modules:

  • Half Adder
  • Full Adder
  • Ripple Carry Adder
  • Subtractor
  • Multiplier
  • Divider

• Logical Modules:

  • AND Gate
  • OR Gate
  • NOT Gate
  • XOR Gate
  • NAND Gate
  • NOR Gate
  • XNOR Gate

• Sequential Modules:

  • D Flip-Flop
  • JK Flip-Flop
  • T Flip-Flop
  • SR Flip-Flop
  • Registers
  • Counters

• Memory Modules:

  • RAM
  • ROM

• Miscellaneous Modules:

  • Multiplexer
  • Demultiplexer
  • Encoder
  • Decoder
  • ALU (Arithmetic Logic Unit)

Note: For a complete list and detailed code, please visit the cheat sheet website.

Accessing the Cheat Sheet

You can access the interactive cheat sheet through the following GitHub Pages link:

Cheatsheet For All Verilog Code

Usage Instructions

1. Navigate to the Cheat Sheet: Visit the Cheatsheet For All Verilog Code.

2. Select the Desired Module: Click on the topic corresponding to the Verilog code you need. This will direct you to the specific code snippet.

3. Copy the Code: In the coding area, click the "Copy" button located at the top-right corner to copy the entire code to your clipboard.

4. Integrate into Your Project: Paste the copied code into your Verilog project as needed.

Advice: For optimal viewing and navigation, it is recommended to access the cheat sheet on a laptop or desktop.

Contributing

Contributions to enhance this repository are welcome. If you have additional Verilog modules or improvements to existing codes, please fork the repository, make your changes, and submit a pull request.

License

This project is licensed under the MIT License. See the LICENSE file for more details.