[DoNotMerge] Add signal trace capability to arcilator

include/circt/Conversion/ArcToLLVM.h

@@ -10,13 +10,20 @@
 #define CIRCT_CONVERSION_ARCTOLLVM_H
 
 #include "circt/Support/LLVM.h"
+#include "llvm/ADT/StringRef.h"
+
 #include <memory>
 
 namespace circt {
 #define GEN_PASS_DECL_LOWERARCTOLLVM
 #include "circt/Conversion/Passes.h.inc"
 
 std::unique_ptr<OperationPass<ModuleOp>> createLowerArcToLLVMPass();
+
+namespace arc {
+constexpr StringLiteral
+    globalRegisterTraceLibrarySymName("_arc_register_trace_library");
+}
 } // namespace circt
 
 #endif // CIRCT_CONVERSION_ARCTOLLVM_H

include/circt/Dialect/Arc/ArcAttributes.h

@@ -0,0 +1,19 @@
+//===- ArcAttributes.h - Declare Arc dialect attributes ----------*- C++-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef CIRCT_DIALECT_ARC_ARCATTRIBUTES_H
+#define CIRCT_DIALECT_ARC_ARCATTRIBUTES_H
+
+#include "mlir/IR/Attributes.h"
+#include "mlir/IR/BuiltinAttributes.h"
+#include "mlir/IR/BuiltinTypes.h"
+
+#define GET_ATTRDEF_CLASSES
+#include "circt/Dialect/Arc/ArcAttributes.h.inc"
+
+#endif // CIRCT_DIALECT_ARC_ARCATTRIBUTES_H

include/circt/Dialect/Arc/ArcAttributes.td

@@ -0,0 +1,25 @@
+//===- ArcAttributes.td - Attributes for Arc dialect -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef CIRCT_DIALECT_ARC_ARCATTRIBUTES_TD
+#define CIRCT_DIALECT_ARC_ARCATTRIBUTES_TD
+
+include "circt/Dialect/Arc/ArcDialect.td"
+include "mlir/IR/BuiltinAttributeInterfaces.td"
+
+def TraceTapAttr : AttrDef<ArcDialect, "TraceTap"> {
+  let mnemonic = "trace_tap";
+  let summary = "TODO";
+  let parameters = (ins "mlir::TypeAttr":$sigType, "uint64_t":$stateOffset,
+      "mlir::ArrayAttr":$names);
+  let assemblyFormat = "`<` $sigType `,` $stateOffset `,` $names `>`";
+}
+
+def TraceTapArrayAttr : TypedArrayAttrBase<TraceTapAttr, "TODO"> {}
+
+#endif // CIRCT_DIALECT_ARC_ARCATTRIBUTES_TD

include/circt/Dialect/Arc/ArcDialect.td

@@ -21,9 +21,11 @@ def ArcDialect : Dialect {
 
   let hasConstantMaterializer = 1;
   let useDefaultTypePrinterParser = 1;
+  let useDefaultAttributePrinterParser = 1;
 
   let extraClassDeclaration = [{
     void registerTypes();
+    void registerAttributes();
   }];
 }
 

include/circt/Dialect/Arc/ArcOps.h

@@ -18,6 +18,7 @@
 #include "mlir/Interfaces/InferTypeOpInterface.h"
 #include "mlir/Interfaces/SideEffectInterfaces.h"
 
+#include "circt/Dialect/Arc/ArcAttributes.h"
 #include "circt/Dialect/Arc/ArcDialect.h"
 #include "circt/Dialect/Arc/ArcTypes.h"
 #include "circt/Dialect/Seq/SeqTypes.h"

include/circt/Dialect/Arc/ArcOps.td

@@ -9,6 +9,7 @@
 #ifndef CIRCT_DIALECT_ARC_ARCOPS_TD
 #define CIRCT_DIALECT_ARC_ARCOPS_TD
 
+include "circt/Dialect/Arc/ArcAttributes.td"
 include "circt/Dialect/Arc/ArcDialect.td"
 include "circt/Dialect/Arc/ArcInterfaces.td"
 include "circt/Dialect/Arc/ArcTypes.td"
@@ -589,13 +590,11 @@ def StateWriteOp : ArcOp<"state_write", [
   StateAndValueTypesMatch<"state", "value">,
 ]> {
   let summary = "Update a state's value";
-  let arguments = (ins
-    StateType:$state,
-    AnyType:$value,
-    Optional<I1>:$condition
-  );
+  let arguments = (ins StateType:$state, AnyType:$value,
+      Optional<I1>:$condition, OptionalAttr<StrAttr>:$traceTapModel,
+      OptionalAttr<IndexAttr>:$traceTapIndex);
   let assemblyFormat = [{
-    $state `=` $value (`if` $condition^)? attr-dict `:` type($state)
+    $state `=` $value (`if` $condition^)?  (`tap` $traceTapModel`[`$traceTapIndex^`]` )? attr-dict `:` type($state)
   }];
 }
 
@@ -707,8 +706,8 @@ def SimEmitValueOp : ArcOp<"sim.emit"> {
 //===----------------------------------------------------------------------===//
 
 def TapOp : ArcOp<"tap"> {
-  let summary = "A tracker op to observe a value under a given name";
-  let arguments = (ins AnyType:$value, StrAttr:$name);
+  let summary = "A tracker op to observe a value under one or more given names";
+  let arguments = (ins AnyType:$value, StrArrayAttr:$names);
   let assemblyFormat = [{ $value attr-dict `:` type($value) }];
 }
 
@@ -721,10 +720,10 @@ def ModelOp : ArcOp<"model", [
     A model with stratified clocks. The `io` optional attribute
     specifies the I/O of the module associated to this model.
   }];
-  let arguments = (ins SymbolNameAttr:$sym_name,
-                       TypeAttrOf<ModuleType>:$io,
-                       OptionalAttr<FlatSymbolRefAttr>:$initialFn,
-                       OptionalAttr<FlatSymbolRefAttr>:$finalFn);
+  let arguments = (ins SymbolNameAttr:$sym_name, TypeAttrOf<ModuleType>:$io,
+      OptionalAttr<FlatSymbolRefAttr>:$initialFn,
+      OptionalAttr<FlatSymbolRefAttr>:$finalFn,
+      OptionalAttr<TraceTapArrayAttr>:$traceTaps);
   let regions = (region SizedRegion<1>:$body);
 
   let assemblyFormat = [{

include/circt/Dialect/Arc/ArcPasses.h

@@ -27,7 +27,6 @@ namespace arc {
 
 std::unique_ptr<mlir::Pass>
 createAddTapsPass(const AddTapsOptions &options = {});
-std::unique_ptr<mlir::Pass> createAllocateStatePass();
 std::unique_ptr<mlir::Pass> createArcCanonicalizerPass();
 std::unique_ptr<mlir::Pass> createDedupPass();
 std::unique_ptr<mlir::Pass> createFindInitialVectorsPass();

include/circt/Dialect/Arc/ArcPasses.td

@@ -26,8 +26,10 @@ def AddTaps : Pass<"arc-add-taps", "mlir::ModuleOp"> {
 
 def AllocateState : Pass<"arc-allocate-state", "arc::ModelOp"> {
   let summary = "Allocate and layout the global simulation state";
-  let constructor = "circt::arc::createAllocateStatePass()";
   let dependentDialects = ["arc::ArcDialect"];
+  let options = [Option<"insertTraceTaps", "trace-taps", "bool", "false",
+                        "Insert TraceTap attributes for tracing">,
+  ];
 }
 
 def ArcCanonicalizer : Pass<"arc-canonicalizer", "mlir::ModuleOp"> {
@@ -42,6 +44,10 @@ def ArcCanonicalizer : Pass<"arc-canonicalizer", "mlir::ModuleOp"> {
   ];
 }
 
+def CombineTaps : Pass<"arc-combine-taps", "mlir::ModuleOp"> {
+  let summary = "Combine taps observing the same value";
+}
+
 def Dedup : Pass<"arc-dedup", "mlir::ModuleOp"> {
   let summary = "Deduplicate identical arc definitions";
   let description = [{
@@ -209,7 +215,7 @@ def LowerVectorizations : Pass<"arc-lower-vectorizations", "mlir::ModuleOp"> {
     This pass lowers `arc.vectorize` operations. By default, the operation will
     be fully lowered (i.e., the op disappears in the IR). Alternatively, it can
     be partially lowered.
-    
+
     The "mode" pass option allows to only lower the boundary, only the body, or
     only inline the body given that both the boundary and the body are already
     lowered.

include/circt/Dialect/Arc/CMakeLists.txt

@@ -14,6 +14,11 @@ mlir_tablegen(ArcEnums.cpp.inc -gen-enum-defs)
 add_public_tablegen_target(CIRCTArcEnumsIncGen)
 add_dependencies(circt-headers CIRCTArcEnumsIncGen)
 
+mlir_tablegen(ArcAttributes.h.inc -gen-attrdef-decls -attrdefs-dialect=arc)
+mlir_tablegen(ArcAttributes.cpp.inc -gen-attrdef-defs -attrdefs-dialect=arc)
+add_public_tablegen_target(CIRCTArcAttributesIncGen)
+add_dependencies(circt-headers CIRCTArcAttributesIncGen)
+
 set(LLVM_TARGET_DEFINITIONS ArcInterfaces.td)
 mlir_tablegen(ArcInterfaces.h.inc -gen-op-interface-decls)
 mlir_tablegen(ArcInterfaces.cpp.inc -gen-op-interface-defs)

integration_test/arcilator/JIT/basic.mlir

@@ -1,4 +1,7 @@
 // RUN: arcilator %s --run --jit-entry=main | FileCheck %s
+// RUN: arcilator %s --observe-wires --observe-registers --observe-ports --trace-taps --run --jit-entry=main | FileCheck %s
+// RUN: arcilator %s --observe-wires --observe-registers --observe-ports --trace-taps --run --jit-entry=main --jit-vcd | FileCheck %s
+// RUN: arcilator %s --observe-wires --observe-registers --observe-ports --trace-taps --run --jit-entry=main --jit-vcd && cat adder.vcd | FileCheck %s --match-full-lines --check-prefix VCD
 // REQUIRES: arcilator-jit
 
 // CHECK: output = 5
@@ -15,12 +18,36 @@ func.func @main() {
   arc.sim.instantiate @adder as %model {
     arc.sim.set_input %model, "a" = %two : i8, !arc.sim.instance<@adder>
     arc.sim.set_input %model, "b" = %three : i8, !arc.sim.instance<@adder>
-    
+
     arc.sim.step %model : !arc.sim.instance<@adder>
-  
+
     %res = arc.sim.get_port %model, "c" : i8, !arc.sim.instance<@adder>
     arc.sim.emit "output", %res : i8
   }
 
   return
 }
+
+
+// VCD:      $date
+// VCD-NEXT:    October 21, 2015
+// VCD-NEXT: $end
+// VCD-NEXT: $version
+// VCD-NEXT:    Some cryptic JIT MLIR magic
+// VCD-NEXT: $end
+// VCD-NEXT: $timescale 1ns $end
+// VCD-NEXT: $scope module adder $end
+// VCD-NEXT:  $var wire 8 ! a $end
+// VCD-NEXT:  $var wire 8 " b $end
+// VCD-NEXT:  $var wire 8 # c $end
+// VCD-NEXT: $upscope $end
+// VCD-NEXT: $enddefinitions $end
+// VCD-NEXT: #0
+// VCD-NEXT: b00000000 !
+// VCD-NEXT: b00000000 "
+// VCD-NEXT: b00000000 #
+// VCD-NEXT: #1
+// VCD-NEXT: b00000010 !
+// VCD-NEXT: b00000011 "
+// VCD-NEXT: b00000101 #
+// VCD-NEXT: #2

integration_test/arcilator/JIT/initial-shift-reg.mlir

@@ -1,4 +1,6 @@
 // RUN: arcilator %s --run --jit-entry=main | FileCheck %s
+// RUN: arcilator %s --observe-wires --observe-registers --observe-ports --trace-taps --run --jit-entry=main --jit-vcd | FileCheck %s
+// RUN: arcilator %s --observe-wires --observe-registers --observe-ports --trace-taps --run --jit-entry=main --jit-vcd && cat shiftreg.vcd | FileCheck %s --match-full-lines --check-prefix VCD
 // REQUIRES: arcilator-jit
 
 // CHECK-LABEL: output = ca
@@ -20,7 +22,7 @@ module {
     hw.output %srC : i8
   }
 
-  func.func @main() {
+  func.func public @main() {
     %ff = arith.constant 0xFF : i8
     %false = arith.constant 0 : i1
     %true = arith.constant 1 : i1
@@ -68,3 +70,64 @@ module {
     return
   }
 }
+
+// VCD:      $date
+// VCD-NEXT:     October 21, 2015
+// VCD-NEXT: $end
+// VCD-NEXT: $version
+// VCD-NEXT:     Some cryptic JIT MLIR magic
+// VCD-NEXT: $end
+// VCD-NEXT: $timescale 1ns $end
+// VCD-NEXT: $scope module shiftreg $end
+// VCD-NEXT:  $var wire 1 ! clock $end
+// VCD-NEXT:  $var wire 8 $ din $end
+// VCD-NEXT:  $var wire 8 ' dout $end
+// VCD-NEXT:  $var wire 1 # en $end
+// VCD-NEXT:  $var wire 1 " reset $end
+// VCD-NEXT:  $var wire 8 ( srA $end
+// VCD-NEXT:  $var wire 8 & srB $end
+// VCD-NEXT:  $var wire 8 % srC $end
+// VCD-NEXT: $upscope $end
+// VCD-NEXT: $enddefinitions $end
+// VCD-NEXT: #0
+// VCD-NEXT: 0!
+// VCD-NEXT: 0"
+// VCD-NEXT: 0#
+// VCD-NEXT: b00000000 $
+// VCD-NEXT: b00000000 %
+// VCD-NEXT: b00000000 &
+// VCD-NEXT: b00000000 '
+// VCD-NEXT: b00000000 (
+// VCD-NEXT: #1
+// VCD-NEXT: b11111110 (
+// VCD-NEXT: b11001010 %
+// VCD-NEXT: #2
+// VCD-NEXT: b11001010 '
+// VCD-NEXT: #3
+// VCD-NEXT: 1!
+// VCD-NEXT: b11111111 $
+// VCD-NEXT: #4
+// VCD-NEXT: 0!
+// VCD-NEXT: #5
+// VCD-NEXT: 1!
+// VCD-NEXT: 1#
+// VCD-NEXT: b00000000 %
+// VCD-NEXT: b00000000 '
+// VCD-NEXT: b11111111 (
+// VCD-NEXT: b11111110 &
+// VCD-NEXT: #6
+// VCD-NEXT: 0!
+// VCD-NEXT: #7
+// VCD-NEXT: 1!
+// VCD-NEXT: b11111110 %
+// VCD-NEXT: b11111110 '
+// VCD-NEXT: b11111111 &
+// VCD-NEXT: #8
+// VCD-NEXT: 0!
+// VCD-NEXT: #9
+// VCD-NEXT: 1!
+// VCD-NEXT: b11111111 %
+// VCD-NEXT: b11111111 '
+// VCD-NEXT: #10
+// VCD-NEXT: 0!
+// VCD-NEXT: #11