CS 254: Assignment 6

Team Members:
1. Devansh Jain  (190100044)
2. Harshit Varma (190100055)

File Descriptions:

Q1:
    TwobitUpCount.vhd       : 2-bit Synchronous Counter
    DFlipFlop.vhd           : D-Flipflops (Storage Element) using behavioural code
    NotGate.vhd             : NOT Gate using 2x1 MUX
    XorGate.vhd             : XOR Gate using 2x1 MUXes
    TwoByOneMux.vhd         : 2x1 MUX using structural modelling
    waveform.jpg            : The simulation result
    paperwork.pdf           : Contains all paperwork - FSM diagrams, STGs and Karnaugh maps
    
Q2:
    ThreebitUpDownCount.vhd : 3-bit Synchronous up/down Counter
    DFlipFlop.vhd           : D-Flipflops (Storage Element) using behavioural code
    Delta2.vhd              : Delta2 Function
    Delta1.vhd              : Delta1 Function
    NotGate.vhd             : NOT Gate using structural modelling
    AndGate.vhd             : AND Gate using structural modelling
    AndGate3.vhd            : 3-input AND Gate using structural modelling
    OrGate.vhd              : OR Gate using structural modelling
    XorGate.vhd             : XOR Gate using structural modelling
    waveform.jpg            : The simulation result
    paperwork.pdf           : Contains all paperwork - FSM diagrams, STGs and Karnaugh maps