This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.
reinforcement-learning deep-learning mcts logic-synthesis electronic-design-automation boolean-optimization electronic-design mcts-agents iclr2024 abc-rl retrieval-guided-rl boolean-circuit-minimization ml-for-logic-synthesis ml-for-chip-design
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Updated
May 10, 2024 - Verilog