bram

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Here are 20 public repositories matching this topic...

noscene / ice40_audio

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verilog example to drive PCM5102 DAC with FPGA

audio fpga verilog icestorm oscillator ice40 bram i2s additive-synthesis ad7606 sinwave pcm5102 ice40up5k

Updated Apr 30, 2018
C

bselimoglu / SoC-ZedBoard-Zynq-7000-Labs

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Hardware and Software Co-design implementations

sdk gpio fsm ddr zedboard dma bram axi zynq-7000 vivado-ip-integrator arm-cortex-a9 zynq7-ps high-performance-port

Updated Dec 5, 2019

dpretet / meduram

Sponsor

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Multi-port BRAM IP for ASIC and FPGA

block asic fpga ram yosys iverilog fusesoc bram amba axi4 axi4-lite multi-port svut axi4-lite-interface

Updated Apr 21, 2021
SystemVerilog

DECAfpga / Arcade_Galaga

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Galaga Arcade Core

fpga bram arcades

Updated Aug 4, 2023
VHDL

Harshp1802 / Fake-Currency-Detector

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Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB

matlab detection vhdl verilog bram fpga-programming basys3-fpga fake-currency block-ram

Updated Sep 30, 2020
VHDL

praveenVnktsh / Hardware-Accelerated-Motion-Estimation-using-FSBM-and-FPGA

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FPGA Implementation of Full Search Block matching using an asynchronous handshake based FSM.

python fpga pixels vhdl motion estimation hdl vga verilog-hdl motion-estimation basys3 bram coe basys3-fpga macroblock

Updated Nov 2, 2020
VHDL

behzadsalami / FPGA-BRAMs-Undervoltig-Study

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Experimental study and analysis on the effect of aggressive voltage underscaling on the reliability of COTS FPGAs: https://ieeexplore.ieee.org/abstract/document/8574581/

fpga reliability sram xilinx voltage resilience fault xilinx-fpga bram voltage-scaling

Updated Feb 22, 2019

samarthaggarwal / ARM-based-multicycle-processor-VHDL

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Processor supporting ARM architecture made in VHDL as a part of COL216 - Computer Architecture

arm vhdl bram multicycle-processor

Updated Jun 24, 2018
VHDL

fcayci / xilinx_vga_framebuffer_ip_core

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VGA IP Core using a dual-port BRAM as a frame buffer (shared BRAM access)

vhdl framebuffer xilinx vga vga-ip bram

Updated May 2, 2014
VHDL

DECAfpga / Arcade_Pooyan

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Arcade Pooyan core

fpga bram arcades sockit

Updated May 14, 2022
VHDL

SUHANI102003 / MEMORIES

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This repository contains the verilog codes for writing memories, especially RAM (single, dual, 3 port) using multiple methods in VIVADO DESIGN SUITE 2020.2

ram bram single-port dual-port distributed-ram ip-method language-template macro-cells